Phase change technology is promising for next generation memories. It uses chalcogenide semiconductors for storing states. The chalcogenide semiconductors, also called phase change materials, have a crystalline state and an amorphous state. In the crystalline state, the phase change materials have a low resistivity, while in the amorphous state they have a high resistivity. The resistivity ratios of the phase change materials in the amorphous and crystalline states are typically greater than 1000 and thus the phase change memory devices are unlikely to have errors for reading states. The chalcogenide materials are stable at certain temperature ranges in both crystalline and amorphous states and can be switched back and forth between the two states by electric pulses. One type of memory device that uses the principal of phase change in chalcogenide semiconductors is commonly referred to as phase change random access memory (PRAM).
PRAM is a promising candidate for next generation memory due to several operating and engineering advantages, including high speed, low power, non-volatility, high density and low cost. PRAM has several advantages over other types of memory such as DRAM, SRAM, and Flash memory. For example, PRAM devices are non-volatile and may be written to with high speed, e.g., less than about 50 nanoseconds. Since transistors are not necessary to accomplish read and write operations, the memory cells may be formed at a high density. In addition, PRAM memory cells are compatible with CMOS logic and can generally be produced at low cost compared to other types of memory cells.
FIG. 1 illustrates a conventional bottom contact PRAM cell. A phase change material 2 is formed between a top electrode 4 and a bottom electrode contact 6. The phase change material 2 is heated up to a temperature higher than the melting temperature when a current passes through it. The temperature is then quickly dropped below the crystallization temperature. A portion of the phase change material, as shown in region 8, is changed to an amorphous state with high resistivity, thus the state of the PRAM cell is changed to a high resistance state. Region 8 can be reset back to crystalline state by heating up the phase change material 2 to a temperature higher than the crystallization temperature, but below the melting temperature, for a certain period.
One engineering challenge in improving PRAM devices is to reduce the programming current required to effectuate the reversible phase change. In general, assuming a given resistivity of the phase change material, a smaller electrode contact area produces a higher resistance and therefore a higher level of resistive heating (Joule heating) for a given applied writing (drive) current. Therefore, a smaller electrode contact area to the phase change material will correspondingly and desirably reduce drive current and thereby power consumption.
As a result, prior art methods of producing PRAM have attempted to reduce the electrode contact area, as the contact area scales with the phase change (information recording) element volume and therefore a required programming current. While certain prior art methods have been successful in reducing a contact area, process window limits on lithographic and etching processes have placed a lower limit on the achievable size of the contact area.
Other approaches have focused on changing the geometry of the contact in order to reduce the contact area. FIG. 2 illustrates a phase change memory device having an edge contact. A phase change material 12 has a contact region 20 with an edge of a bottom electrode 14. Since it is easy to form a very thin bottom electrode 14, the contact region 20 can have a small area, such as about 0.004 μm2. Therefore, the current density is significantly improved. However, such an approach requires complex and costly manufacturing processes. For example, in order to form the side contact region 20, the bottom electrode 14 is deposited and patterned followed by the deposition of an inter-layer dielectric (ILD) 15. A trench 18 is formed in the ILD 15 downward into an insulating layer 22 in order to expose the side edge 20 of the bottom electrode 14. This prior art embodiment requires at least two masking (patterning) steps, one for the formation of the bottom electrode 14 and one for the formation of the trench 18.
Thus, there is a need in the memory device manufacturing art for an improved PRAM device and a method for forming the same to reduce processing steps and achieve lower production costs.